Verilog
https://www.youtube.com/watch?v=2IReMT_zjK8
Verilog Modelling Styles
Can be done in three different abstractions:
- Gate level [less abstract]
- Dataflow level [more abstract]
- Behavioral level [even more abstract]
Combinational Logic vs Sequential Logic
Combinational Logic
Output is a function of the input
2 to 1 multiplexer
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Gate level Describes the actual gate and how they are connected
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Dataflow level Describes the flow of data in the circuit
-
Behavioral level describes the behavior, rather than what the circuit is
Sequential Logic
Requires:
- memory
- state